VECTREX_XLINK Project Status
Project File: vectrex_xlink.ise Current State: Programming File Generated
Module Name: vectrex_xlink
  • Errors:
No Errors
Target Device: xc2v1000-4fg456
  • Warnings:
162 Warnings
Product Version: ISE 9.2.03i
  • Updated:
Wed Jan 18 20:30:47 2012
 
VECTREX_XLINK Partition Summary
No partition information was found.
 
Device Utilization Summary
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 836 10,240 8%  
Number of 4 input LUTs 3,438 10,240 33%  
Logic Distribution     
Number of occupied Slices 2,073 5,120 40%  
Number of Slices containing only related logic 2,073 2,073 100%  
Number of Slices containing unrelated logic 0 2,073 0%  
Total Number of 4 input LUTs 3,521 10,240 34%  
Number used as logic 3,438      
Number used as a route-thru 81      
Number used as Shift registers 2      
Number of bonded IOBs 36 324 11%  
    IOB Flip Flops 10      
Number of Block RAMs 11 40 27%  
Number of GCLKs 4 16 25%  
Number of DCMs 1 8 12%  
Total equivalent gate count for design 758,039      
Additional JTAG gate count for IOBs 1,728      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Jan 18 20:29:32 20120153 Warnings12 Infos
Translation ReportCurrentWed Jan 18 20:29:36 2012000
Map ReportCurrentWed Jan 18 20:29:44 201205 Warnings2 Infos
Place and Route ReportCurrentWed Jan 18 20:30:33 201203 Warnings3 Infos
Static Timing ReportCurrentWed Jan 18 20:30:37 2012003 Infos
Bitgen ReportCurrentWed Jan 18 20:30:46 201201 Warning0