Xilinx Design Summary

BWIDOW_XLINK Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	933	10,240	9%
Number of 4 input LUTs	1,791	10,240	17%
Logic Distribution
Number of occupied Slices	1,205	5,120	23%
Number of Slices containing only related logic	1,205	1,205	100%
Number of Slices containing unrelated logic	0	1,205	0%
Total Number of 4 input LUTs	1,907	10,240	18%
Number used as logic	1,791
Number used as a route-thru	96
Number used as Shift registers	20
Number of bonded IOBs	36	324	11%
IOB Flip Flops	6
Number of Block RAMs	24	40	60%
Number of GCLKs	2	16	12%
Number of DCMs	1	8	12%
Total equivalent gate count for design	1,601,638
Additional JTAG gate count for IOBs	1,728

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met