Xilinx Design Summary

VECTREX_ISE Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Total Number Slice Registers	914	10,240	8%
Number used as Flip Flops	835
Number used as Latches	79
Number of 4 input LUTs	3,497	10,240	34%
Logic Distribution
Number of occupied Slices	2,105	5,120	41%
Number of Slices containing only related logic	2,105	2,105	100%
Number of Slices containing unrelated logic	0	2,105	0%
Total Number of 4 input LUTs	3,619	10,240	35%
Number used as logic	3,497
Number used as a route-thru	121
Number used as Shift registers	1
Number of bonded IOBs	17	324	5%
IOB Flip Flops	6
Number of Block RAMs	15	40	37%
Number of MULT18X18s	8	40	20%
Number of GCLKs	5	16	31%
Number of DCMs	1	8	12%
Total equivalent gate count for design	1,054,076
Additional JTAG gate count for IOBs	816

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met