VECTREX_XLINK Project Status
Project File: vectrex_xlink.ise Current State: Programming File Generated
Module Name: vectrex_xlink
  • Errors:
No Errors
Target Device: xc2v1000-4fg456
  • Warnings:
207 Warnings
Product Version: ISE 9.2.03i
  • Updated:
Mon Jan 30 20:40:07 2012
 
VECTREX_XLINK Partition Summary
No partition information was found.
 
Device Utilization Summary
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 980 10,240 9%  
Number of 4 input LUTs 2,966 10,240 28%  
Logic Distribution     
Number of occupied Slices 1,863 5,120 36%  
Number of Slices containing only related logic 1,863 1,863 100%  
Number of Slices containing unrelated logic 0 1,863 0%  
Total Number of 4 input LUTs 3,164 10,240 30%  
Number used as logic 2,966      
Number used as a route-thru 196      
Number used as Shift registers 2      
Number of bonded IOBs 38 324 11%  
    IOB Flip Flops 11      
Number of Block RAMs 9 40 22%  
Number of MULT18X18s 1 40 2%  
Number of GCLKs 4 16 25%  
Number of DCMs 1 8 12%  
Total equivalent gate count for design 630,741      
Additional JTAG gate count for IOBs 1,824      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Jan 30 20:38:49 20120198 Warnings13 Infos
Translation ReportCurrentMon Jan 30 20:38:54 2012000
Map ReportCurrentMon Jan 30 20:39:03 201205 Warnings2 Infos
Place and Route ReportCurrentMon Jan 30 20:39:54 201203 Warnings3 Infos
Static Timing ReportCurrentMon Jan 30 20:39:58 2012003 Infos
Bitgen ReportCurrentMon Jan 30 20:40:07 201201 Warning0