VECTREX_XLINK Project Status | |||
Project File: | vectrex_xlink.ise | Current State: | Programming File Generated |
Module Name: | vectrex_xlink |
|
No Errors |
Target Device: | xc2v1000-4fg456 |
|
172 Warnings |
Product Version: | ISE 9.2.03i |
|
Sat Jan 21 19:27:08 2012 |
VECTREX_XLINK Partition Summary | |||
No partition information was found. |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops | 856 | 10,240 | 8% | |
Number of 4 input LUTs | 2,662 | 10,240 | 25% | |
Logic Distribution | ||||
Number of occupied Slices | 1,642 | 5,120 | 32% | |
Number of Slices containing only related logic | 1,642 | 1,642 | 100% | |
Number of Slices containing unrelated logic | 0 | 1,642 | 0% | |
Total Number of 4 input LUTs | 2,740 | 10,240 | 26% | |
Number used as logic | 2,662 | |||
Number used as a route-thru | 76 | |||
Number used as Shift registers | 2 | |||
Number of bonded IOBs | 36 | 324 | 11% | |
IOB Flip Flops | 10 | |||
Number of Block RAMs | 5 | 40 | 12% | |
Number of MULT18X18s | 1 | 40 | 2% | |
Number of GCLKs | 4 | 16 | 25% | |
Number of DCMs | 1 | 8 | 12% | |
Total equivalent gate count for design | 364,405 | |||
Additional JTAG gate count for IOBs | 1,728 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | Sat Jan 21 19:25:58 2012 | 0 | 162 Warnings | 15 Infos |
Translation Report | Current | Sat Jan 21 19:26:03 2012 | 0 | 0 | 0 |
Map Report | Current | Sat Jan 21 19:26:09 2012 | 0 | 6 Warnings | 2 Infos |
Place and Route Report | Current | Sat Jan 21 19:26:56 2012 | 0 | 3 Warnings | 3 Infos |
Static Timing Report | Current | Sat Jan 21 19:26:59 2012 | 0 | 0 | 3 Infos |
Bitgen Report | Current | Sat Jan 21 19:27:07 2012 | 0 | 1 Warning | 0 |