VECTREX_XLINK Project Status
Project File: vectrex_xlink.ise Current State: Programming File Generated
Module Name: vectrex_xlink
  • Errors:
No Errors
Target Device: xc2v1000-4fg456
  • Warnings:
172 Warnings
Product Version: ISE 9.2.03i
  • Updated:
Sat Jan 21 19:27:08 2012
 
VECTREX_XLINK Partition Summary
No partition information was found.
 
Device Utilization Summary
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 856 10,240 8%  
Number of 4 input LUTs 2,662 10,240 25%  
Logic Distribution     
Number of occupied Slices 1,642 5,120 32%  
Number of Slices containing only related logic 1,642 1,642 100%  
Number of Slices containing unrelated logic 0 1,642 0%  
Total Number of 4 input LUTs 2,740 10,240 26%  
Number used as logic 2,662      
Number used as a route-thru 76      
Number used as Shift registers 2      
Number of bonded IOBs 36 324 11%  
    IOB Flip Flops 10      
Number of Block RAMs 5 40 12%  
Number of MULT18X18s 1 40 2%  
Number of GCLKs 4 16 25%  
Number of DCMs 1 8 12%  
Total equivalent gate count for design 364,405      
Additional JTAG gate count for IOBs 1,728      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat Jan 21 19:25:58 20120162 Warnings15 Infos
Translation ReportCurrentSat Jan 21 19:26:03 2012000
Map ReportCurrentSat Jan 21 19:26:09 201206 Warnings2 Infos
Place and Route ReportCurrentSat Jan 21 19:26:56 201203 Warnings3 Infos
Static Timing ReportCurrentSat Jan 21 19:26:59 2012003 Infos
Bitgen ReportCurrentSat Jan 21 19:27:07 201201 Warning0